1. Field of the Invention
The invention relates to an IC tester and operation method thereof, and more particularly, to an IC tester for preventing damage to a device-under-test, DUT, from electrostatic discharge (ESD) and operation method thereof, wherein the IC tester refers to any commercial reliability analyzer.
2. Description of the Prior Art
For the process of manufacturing IC chips, the reliability of products is a very important factor. Reliability is defined as the lifetime of a product under normal conditions. The IC chip makers need to know the lifetime of products in a short time, so an accelerated lifetime test is used to forecast the average lifetime. The theorem of the accelerated lifetime test is to test the lifetime of products in a harsh condition, such as with high temperature or great pressure environment, high voltage, or high current; then use the lifetime model to calculate real lifetime under normal conditions. Typical reliability tests are divided into wafer-level reliability (WLR) tests and package-level reliability (PLR) tests. The WLR test means to test the wafer directly on a tester in a production line. The PLR test means to segment and package a wafer as devices-under-test (DUT), and to insert those devices-under-test into a DUT board to test in a high temperature oven. The stress condition of the PLR test is closer to normal conditions of products, and the test result is widely accepted by manufactures.
A typical IC PLR tester is illustrated in FIG. 1, which is a schematic diagram of an IC tester 10 according to the prior art. The IC tester 10 contains a temperature control oven chamber 12 and one or two layers of heat-resistance material 20, such as rubber. The thermal-isolated material 20 is fixed in the oven door 14 and cannot be moved for isolating a temperature of the temperature control oven chamber 12. The heat-resistance material 20 has a plurality of sliced crevices 22, therefore a plurality of DUT boards 18 can pass through the sliced crevices 22 to load on the oven door 14. An IC tester 10 according to the prior art usually further contains an assemblage of circuit contacts (not shown in FIG. 1) positioned outside of the oven door 14 for connecting test circuits to perform electric property tests. Steps of executing the IC test according to the prior art include inserting devices-under-test 16 into sockets 26 on the DUT boards 18, loading the DUT boards 18 on the oven door 14 (please refer to FIG. 1), closing the oven door 14, and supplying current, voltage, and high temperature conditions with the temperature control oven to perform the test.
However, there is a vital disadvantage in that the IC tester 10 according to the prior art cannot prevent the damage of DUTs from electrostatic discharge (ESD). When an operator passes the DUT boards 18 through sliced crevices 22 of the thermal-isolated material 20 to load DUT boards 18, the bonding fingers 24 and the electricity-contacting area of the DUT boards 18 will rub against the thermal-isolated material 20 to create ESD, resulting in damage to the DUTs. This means the DUTs may be broken, and will lose regular functionality before the electric property test. Similarly, after performing the test, when the operation unloads the DUT boards 18 from oven door 14, the DUT boards 18 will also rub against the thermal-isolated material 20, creating ESD. The ESD will damage devices and cause huge costs.
The present remedy for a prior-art IC tester is to use specific fixtures provided by the prior-art IC tester maker. An operator needs to isolate the IC devices-under-test one by one with the specific fixtures when setting the devices-under-test into the sockets of the DUT boards. After loading the DUT boards on the oven door, the operator has to take off each specific fixture of every device-under-test for performing the IC test. When the IC test is finished, the operator also needs to isolate each device-under-test with the specific fixtures for unloading the DUT boards. Although the specific fixtures can avoid ESD, it costs too much time by putting on and taking off the specific fixtures. Furthermore, with the heavy and complicated steps of the remedy, negligence may be caused by the operator, resulting damage to the devices-under-test. Thus the purpose of decreasing the cost and improving the effects of the IC test is still not achieved. As a result, an IC tester for preventing damage from ESD with simple related operation method is badly needed by IC makers.